This invention is in the field of audio amplifiers, and is more specifically directed to digital pulse-coded-modulation to pulse-width-modulation type class D audio power amplifiers.
In recent years, digital signal processing techniques have become prevalent in many electronic systems. The fidelity provided by digital techniques has increased dramatically with the switching speed of digital circuits. In audio applications, the sampling rates of modern digital signal processing are sufficiently fast that digital techniques have become widely accepted for audio electronic applications.
Digital techniques for audio signal processing now extend to the driving of the audio output amplifiers. A new class of amplifier circuits has now become popular in many audio applications, namely “class D” amplifiers. Class D amplifiers drive a complementary output signal that is digital in nature, with the output voltage swinging fully from “rail-to-rail” at a duty cycle that varies with the audio information. Complementary metal-oxide-semiconductor (CMOS) output drive transistors are thus suitable for class D amplifiers, as such devices are capable of high, full-rail, switching rates such as desired for digital applications. As known in the art, CMOS drivers conduct extremely low DC current, and their resulting efficiency is especially beneficial in portable and automotive audio applications, as well as in small form factor systems such as flat-panel LCD, plasma televisions, and DVD receivers. In addition, the ability to realize the audio output amplifier in CMOS enables integration of an audio output amplifier with other circuitry in the audio system, further improving efficiency and also reducing manufacturing cost of the system. This integration also provides performance benefits resulting from close device matching between the output devices and the upstream circuits, and from reduced signal attenuation.
FIG. 1 illustrates the architecture of a conventional class D audio amplifier, specifically a so-called “class AD” audio amplifier with a bridged load, for a single channel (i.e., typically, one of multiple channels in the system). In the example of FIG. 1, an input digital audio signal is received on lines DIN by digital audio processing function 15. Typically, this digital audio signal is in the form of a twenty-four bit pulse-code-modulated (PCM) signal at a sample rate that typically ranges from 44 kHz to 192 kHz, depending on the audio source.
Digital audio processing function 15 applies the appropriate signal processing to the digital audio signal according to the functions of the system. This signal processing can include parametric speaker equalization or “voicing”, implementation of graphic equalizer presets, treble and bass adjustment, precision soft volume control on the audio signal being processed for its channel. Other digital functions that can be performed by digital audio processing function 15 include loudness compensation to boost the bass frequencies when the output for the channel is low, dynamic range compression, background noise floor compensation or noise squelch, center or sub-woofer channel synthesis, programmable dither, peak limiting and clipping, and other digital filter processing. These functions are typically performed by the application of biquad, or second-order IIR, digital filters in a cascade arrangement.
According to this conventional architecture, as is typically in conventional digital audio systems, the PCM input signal is converted to a pulse-width-modulated (PWM) signal so that speaker SPKR is driven by a class D output amplifier. In order to achieve “CD” quality sound while keeping the PWM clock rate reasonable (200 MHz or less), however, a fully digital implementation of the PWM conversion includes interpolation function 17, which oversamples the processed PCM input signal at a rate that is much higher than the input sample rate; as known in the art, this oversampling reduces total harmonic distortion, and maintains harmonics that have significant amplitude outside of the audio band. In addition, noise shaping and digital non-linear correction function 19 processes the oversampled data stream from interpolation function 17. As known in the art, spectral noise-shaping is typically implemented by way of a sigma-delta modulator, resulting in quantization noise that is high-pass shaped to minimize the effects of quantization noise in audible frequencies. Digital non-linear correction, for example by way of Hammerstein modeling and correction that effectively includes simple power expansion of the input signal followed by linear and time-invariant digital filters, effectively compensates for distortion that otherwise is generated in the conversion of variable-amplitude, fixed-duration, PCM signals into fixed-amplitude, variable-duration, PWM signals.
In this conventional architecture of FIG. 1, the output of noise shaping and digital non-linear correction function 19 is an eight-bit digital signal, sampled at a frequency that is on the order of eight times the input sampling frequency (e.g., eight times the input sampling frequency of 48 kHz, or 384 kHz). As shown in FIG. 1b, the timing control is effected in this system by clock circuitry 13, which typically includes a frequency multiplier applied to a crystal oscillator clock signal, in combination with a digital phase-locked loop (PLL). PCM to PWM conversion function 21 generates PWM signals corresponding to the processed audio signal, in the conventional manner.
PCM to PWM conversion function 21 in this conventional class D audio amplifier is preferably implemented by digital circuitry that digitally calculates the times at which rising and falling edges of the PWM output signals are to be issued. In this manner, the reference triangle waveform may simply be a high-speed clock signal. The digital circuitry can simply receive the input PCM signal on line PCM13 in, and digitally calculate the edges of the differential PWM pulses, including the desired filtering. Conventional high-speed digital signal processing circuitry is capable of carrying out these calculations sufficiently rapidly for driving digital audio output PWM signals, as known in the art.
In this conventional audio implementation, audio speaker SPKR is the load, and is bridged between pairs of output transistors 7A, 7C; 7B, 7D, in a class “AD” amplifier arrangement so that a zero input PCM signal will produce a 50% duty cycle output drive across load SPKR. This class AD arrangement is effected by transistors 7A, 7D being turned on while transistors 7B, 7C are off, so that current flows from left-to-right through load SPKR in one half-cycle, and so that transistors 7B, 7C are on while transistors 7A, 7D are off in the other half-cycle, during which current flows from right-to-left through load SPKR. In this arrangement, the common mode voltage across the bridged load SPKR is zero volts. LC filters 23P, 23M may be provided between the H-bridge of 7A, 7C; 7B, 7D and load SPKR.
By way of further background, other class D amplifier arrangements are also known in the art. One such arrangement is referred to as the class “BD” amplifier, by way of analogy to class B analog amplifiers. In the class BD amplifier, the two halves of the H-bridge are driven by separate modulators. As a result, there are three possible drive states across the bridged load: full positive polarity, full negative polarity, and zero volts. As a result, for zero input signal, no output PWM signals appear at all (i.e., there is zero output, or the PWM output is at a “zero” state).
Class D amplifiers have become attractive for audio applications, especially as the desired output power levels have increased over recent years. The efficiency of class D amplifiers in driving loudspeakers can be higher than 90%, which is much higher than the efficiency provided by conventional analog audio amplifiers. Among other benefits of this improved efficiency, the heat that is dissipated in the drive circuitry is much reduced, and thus the amplifier heat sinks can be much smaller (and thereby lighter). Class D audio amplifiers have thus become quite popular for portable and automotive audio systems.
By way of further background, the technique of providing inter-channel delay among multiple audio channels driven by class D amplifiers to reduce noise interference is known in the art. Such a technique is described in U.S. Patent Application Publication US 2002/0060605 A1, which is commonly assigned herewith and incorporated herein by this reference. As described in that Publication, programmable inter-channel delay between audio channels (e.g., left and right channels in a stereo system) can reduce switching noise between the pulse-width-modulated outputs, reduce cross-talk among the multiple channels, and generally provide significant improvement in system performance. More specifically, the inter-channel delay described in this Publication temporally moves the switching times of one channel away from the switching times of other channels, thus reducing peak switching noise levels. And as described in that Publication, and also in U.S. Pat. No. 6,373,336 B1, which is also commonly assigned herewith, programmable delay can be inserted so that the pulse-width-modulated switching times of opposite sides of a full-bridged load within a single channel are not temporally aligned, which also reduces switching noise within a single audio channel.
By way of further background, a particular problem in class D audio amplifiers is presented by the transient events of muting and un-muting of the audio system. As is fundamental in the art, a steady-state square wave time-domain signal (corresponding to a 50% duty cycle PWM signal) transforms into the frequency domain as discrete frequency components at the fundamental “carrier” frequency and its harmonics. It has been observed that if the PWM signal is abruptly gated on or off or otherwise abruptly changes its duty cycle, however, significant energy is present in sidebands to the carrier frequency and its harmonics. And even if the fundamental frequency is relatively high, the abrupt gating on or off of the PWM signal can result in sidebands with significant energy that extend into audible frequencies, which manifest as audible “clicks” or “pops”. In audio systems, this gating on and off of the PWM output occurs when the user mutes or unmutes the audio output, and at power-up and power-down, in which case the audible clicks and pops are very undesirable.
Known techniques for reducing clicks and pops in analog audio amplifiers include smoothing the change in biasing, for example at power-up. However, these smooth biasing changes cannot be directly applied in class D amplifiers, because these amplifiers operate by way of PWM switching of the output transistors. According to another conventional approach, clicks and pops are reduced by introducing a switch or relay that disconnects the load during mode changes, thus eliminating transients from appearing at the load; however, the insertion and control of such a switch or relay has proven to be cost-prohibitive, especially in modern systems.
Considering that class D audio amplifiers effectively operate in the digital realm, and also considering that many sources of audio input signals are also digital in nature (e.g., compact discs, MP3 and other digitally compressed music files, satellite radio), many modern audio systems are fully digital, in that they receive digital input signals and produce digital, PWM, class D amplifier output. In these fully digital systems, digital signal processing techniques for suppressing clicks and pops are known. Examples of these digital techniques are described in U.S. Pat. No. 6,720,825 and in U.S. Patent Application Publication No. US 2004/0017854, assigned to Texas Instruments Incorporated and incorporated herein by this reference.
Referring now to FIGS. 2a and 2b, the architecture of a conventional multiple channel digital audio system, and its operation in implementing both conventional suppression of clicks and pops and also conventional inter-channel delay, will now be described. As shown in FIG. 2a, multi-channel digital signal processing function 15n receives the input audio signals corresponding to n audio channels, and performs the digital signal processing described above relative to function 15 of FIG. 1. Digital signal processing function 15n presents n output signals, in PCM form, to each of n PWM channels 251 through 25n. PWM channels 25 perform the PCM-to-PWM conversion, interpolation filtering, and the like described above relative to FIGS. 1a and 1b, and generate corresponding differential pulse-width-modulated signals on output lines PWM+, PWM−, which are forwarded to a corresponding power stage 27. Each of power stages 271 through 27n include the H-bridge transistors 7A through 7D, as described above relative to FIG. 1, which drive their respective loads SPKR_1 through SPKR_n. In addition, each of PWM channels 251through 25n generate a control signal on line VALID_CH_1 through VALID_CH_n to its respective power stage 271 through 27n. The level present on each line VALID indicates (when active) that its power stage 27 is to respond to the PWM signals on its associated lines PWM+, PWM− and drive load SPKR accordingly; an inactive level on line VALID causes its associated power stage 27 to place its output in an inactive state, regardless of the signals on lines PWM+, PWM−. This inactive state can be a high-impedance condition, in which all switches are turned off to float load SPKR, or can be a short-circuit state in which both terminals to load SPKR are at ground.
In this conventional arrangement, power stages 271 through 27n are realized by separate integrated circuits from integrated circuit 26 that implements PWM channels 251 through 25n (and digital signal processing function 15). An example of a conventional class D amplifier power stage integrated circuit is the TAS5111 Digital Amplifier Power Stage integrated circuit available from Texas Instruments Incorporated, which is designed to drive a single bridged 4 ohm speaker in response to a differential PWM signal for a single channel. A conventional example of integrated circuit 26 that includes digital signal processing function 15n and multiple PWM channels 25 is the TAS5036 Six Channel Digital Audio PWM Processor, also available from Texas Instruments Incorporated. As evident from FIG. 2a, three conductors per audio channel are required, two conductors (PWM+, PWM−) for the PWM signal and one conductor (VALID) for the control or enable signal.
FIG. 2b illustrates a sequence of operation of the system of FIG. 2a, in beginning operation from a muted condition. Prior to time t0 in this example of FIG. 2b, all channels (i.e., both channels in this example) are inactive, as indicated by the low levels on lines VALID_CH_1 and VALID_CH_2. In this example, the signals on lines PWM+ and PWM− for both of channels 1 and 2 are inactive. Only the signals on lines PWM+ are shown in FIG. 2b (by way of lines PWM+_CH_1 and PWM+_CH_2) for the sake of clarity, it being understood that the PWM signals on lines PWM− for each channel are complementary to those on lines PWM+. At time t1, line VALID_CH_1 is taken to a high, active, level, and PWM channel 251 begins issuing a reduced click and pop start sequence on its lines PWM+, PWM−. The specific sequence applied to lines PWM+, PWM− at this time are designed to cancel out transients in audible frequencies that result from the starting of the PWM output. The specific pulses in the start sequence can be selected in the manner described in U.S. Pat. No. 6,720,825 B1, incorporated herein by reference.
In this conventional system, inter-channel delay is provided between the multiple channels in this system, to reduce switching noise between the pulse-width-modulated outputs, reduce cross-talk among the multiple channels, and generally provide significant improvement in system performance, as described in U.S. Patent Publication No. US 2002/0060605 A1 and U.S. Pat. No. 6,373,336 B1, both also incorporated herein by reference. This conventional inter-channel delay is enforced not only for PWM signals but also in the issuing of an active level on the VALID line, as shown in FIG. 2b. This is because the effective signal that is reproduced at the power stage output is a function of the signals on both of the PWM and VALID lines for a single channel. Consequently, both PWM lines and the VALID signal must be shifted in time, by the same delay time, in order to produce a low click and pop start. Accordingly, at time t1, line VALID_CH_2 is taken to an active level to enable power stage 272, following the selected inter-channel delay IC_Δ. The click and pop reducing start sequence then initiates for channel 2, as shown on line PWM+_CH_2; this start sequence corresponds to that applied to channel 1, but is also delayed by the inter-channel delay IC_Δ.
At the end of the start sequence for channel 1, at time t2, PWM channel 251 begins driving lines PWM+, PWM− (shown as line PWM+_CH_1 in FIG. 2b) with an audio signal. For purposes of this description, the audio signal shown in FIG. 2b is a zero level signal, which amounts to a 50% duty cycle on lines PWM+, PWM− because of the class AD arrangement in this example. And after the elapse of the inter-channel delay IC_Δ, at time t3, PWM channel 252 begins driving its PWM signals on lines PWM+, PWM− (shown as line PWM+_CH_2 in FIG. 2b).
According to this conventional approach, therefore, both of the beneficial techniques of inter-channel delay and reduced click and pop start sequences are applied in the multi-channel system. However, as evident from FIG. 2a, this approach requires integrated circuit 26 to have a VALID pin and conductor dedicated to each of its output channels. For example, six VALID pins (and conductor lines) are required for a six-channel audio signal processor. Especially with the continuing trend toward ever-smaller and less power-consumptive audio systems, this large number of pins and conductors is a significant constraint on the ability to reduce the size and form factor of the integrated circuits. The number of pins is especially limited in high power packages, because of the need to safely conduct heat from the packaged integrated circuit. And high pin counts also complicate the layout and construction of the system boards for the audio systems.